Experienced Electronics and ASIC Verification Engineer with extensive expertise in Electronic Design Automation (EDA) tools, pre-silicon and post-silicon verification processes, and regression automation frameworks. Skilled in leveraging artificial intelligence-driven methodologies to optimize verification efficiency. Proficient with industry-standard tools including Cadence EDA, SystemVerilog UVM, and formal verification techniques. Adept at debugging complex electronics systems and committed to mentoring engineering teams to achieve technical excellence.
ASIC Verification and Validation
SystemVerilog and UVM Expertise
Formal Verification (JasperGold, Assertions)
Low-Power Verification (UPF)
Regression Management (vManager)
AI-Driven Verification (Xcelium ML)
Advanced Troubleshooting and Debugging
Programming and Scripting (Python, Tcl, Shell, C, C, VHDL, SystemC)
Agile Project Management and Methodologies
Technical Leadership and Mentorship