Zeeshan Hyder
Stockholm
Summary
Experienced Electronics and ASIC Verification Engineer with extensive expertise in Electronic Design Automation (EDA) tools, pre-silicon and post-silicon verification processes, and regression automation frameworks. Skilled in leveraging artificial intelligence-driven methodologies to optimize verification efficiency. Proficient with industry-standard tools including Cadence EDA, SystemVerilog UVM, and formal verification techniques. Adept at debugging complex electronics systems and committed to mentoring engineering teams to achieve technical excellence.
Overview
13
13
years of professional experience
1
1
Certification
Work History
Principal Application Engineer
Cadence Design Systems
07.2019 - Current
- Company Overview: Cadence verification and digital providing technical support and consulting for Cadence verification tools across Europe
- Providing technical support and consulting for Cadence verification tools across Europe
- Led ASIC verification projects for ARM, Ericsson, and Microchip, achieving 3.5x regression performance gains
- Implemented formal verification frameworks, optimizing fault coverage and safety-critical validation
- Developed AI-driven verification methodologies using Xcelium ML
- Mentored junior engineers across multiple Cadence sites
- Providing support for Cadence Verification tools to various customers in Scandinavia and UK
- New software/tool evaluation for customers
- Carrying out pre-sales activity, tool demos to customers
- Carried out services projects for Cadence customers and help proliferate cadence software
- Acting as a bridge between R&D and customers to fix or improve software features
- Delivered technical presentations within my department
- Cadence verification and digital providing technical support and consulting for Cadence verification tools across Europe
Senior ASIC Developer/Verification Engineer
Ericsson AB
11.2012 - 06.2019
- Led system-level verification for Ericsson’s first dedicated ASIC for 4G/5G technologies, significantly enhancing product reliability and network performance.
- Developed and implemented formal verification methodologies, reducing verification effort by approximately 40%.
- Conducted post-silicon validation using prototype boards and advanced debugging tools, improving fault detection efficiency by 30%.
- Developed automated software tests for network chips, increasing testing efficiency and reducing manual effort by over 50%.
- Successfully spearheaded migration from legacy version control systems to GIT, streamlining code management processes.
- Established continuous integration workflows with Jenkins, automating regression tests and linting checks, and significantly improving code quality and team productivity.
- Provided mentorship and training to over 10 new employees, facilitating their rapid onboarding and technical proficiency.
Embedded Software Researcher
Scania AB
01.2012 - 07.2012
- Developed a robust CAN bus interface integrating Scania truck ECUs with MATLAB Simulink, significantly reducing in-vehicle testing frequency and manual workload.
- Designed and implemented cross-compiled embedded C software for real-time processor-in-the-loop (PIL) simulation, enhancing the accuracy and reliability of ECU validation.
- Supported Scania's compliance with ISO functional safety standards, contributing to safer and more reliable heavy vehicle systems.
Education
Master’s - System-on-Chip Design
KTH Royal Institute of Technology
Stockholm Sweden01-2012
Bachelor’s - Electrical Engineering
UET Taxila
Islamabad, Pakistan01-2009
Skills
ASIC Verification and Validation
SystemVerilog and UVM Expertise
Formal Verification (JasperGold, Assertions)
Low-Power Verification (UPF)
Regression Management (vManager)
AI-Driven Verification (Xcelium ML)
Advanced Troubleshooting and Debugging
Programming and Scripting (Python, Tcl, Shell, C, C, VHDL, SystemC)
Agile Project Management and Methodologies
Technical Leadership and Mentorship
- Advanced Skills in Electronics Engineering
- Training and mentoring
- Agile project management
- Programming languages: C, C, VHDL, System Verilog, System C
- JIRA Project Management
- Agile methodologies
- Advanced Skills in Electronics Engineering
- Training and mentoring
- Agile project management
- Programming languages: C, C, VHDL, System Verilog, System C
- JIRA Project Management
- Agile methodologies
- Advanced Skills in Electronics Engineering
- Training and mentoring
- Agile project management
- Programming languages: C, C, VHDL, System Verilog, System C
- JIRA Project Management
- Agile methodologies
Certification
- SystemVerilog and Universal Verification Methodology (UVM) Certification
- Formal Verification Techniques and Applications
- Cadence EDA Tools Advanced Training
- Artificial Intelligence in Electronic Design Automation
- ASIC Design and Verification Processes
- Post-Silicon Debugging and Validation Workshop
- Regression Automation Framework Development
- Technical Leadership and Engineering Mentorship Training
Languages
English
Native or Bilingual
Swedish
Full Professional
Timeline
Principal Application Engineer
Cadence Design Systems
07.2019 - Current
Senior ASIC Developer/Verification Engineer
Ericsson AB
11.2012 - 06.2019
Embedded Software Researcher
Scania AB
01.2012 - 07.2012
Master’s - System-on-Chip Design
KTH Royal Institute of Technology
Bachelor’s - Electrical Engineering
UET Taxila
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